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US Patent 7304355 Three-dimensional-memory-based self-test integrated circuits and methods

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7304355
Date of Patent
December 4, 2007
Patent Application Number
10772053
Date Filed
February 3, 2004
Patent Citations Received
‌
US Patent 12136562 3D semiconductor device and structure with single-crystal layers
3
‌
US Patent 12094892 3D micro display device and structure
4
‌
US Patent 12120880 3D semiconductor device and structure with logic and memory
5
‌
US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
6
‌
US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding
7
‌
US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path
8
‌
US Patent 11711928 3D memory devices and structures with control circuits
9
‌
US Patent 11763864 3D memory semiconductor devices and structures with bit-line pillars
...
Patent Primary Examiner
‌
Long Pham
Patent abstract

The three-dimensional memory (3D-M) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, 3D-M has minimum impact to the layout of the CUT. The CUT with integrated 3D-M supports IC self-test. Moreover, with a large bandwidth with the CUT, 3DM-based IC self-test enables at-speed test.

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