US Patent 7304355 Three-dimensional-memory-based self-test integrated circuits and methods

The three-dimensional memory (3D-M) can be used to carry the test data and/or test-data seeds for the circuit-under-test (CUT). When integrated with the CUT, 3D-M has minimum impact to the layout of the CUT. The CUT with integrated 3D-M supports IC self-test. Moreover, with a large bandwidth with the CUT, 3DM-based IC self-test enables at-speed test.