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US Patent 7198980 Methods for assembling multiple semiconductor devices

Patent 7198980 was granted and assigned to Micron Technology on April, 2007 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7198980
Date of Patent
April 3, 2007
Patent Application Number
10706576
Date Filed
November 12, 2003
Patent Citations Received
‌
US Patent 12113026 Multi-chip package and method of providing die-to-die interconnects in same
0
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US Patent 11990382 Fine pitch BVA using reconstituted wafer with area array accessible for testing
0
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US Patent RE49987 Multiple plated via arrays of different wire heights on a same substrate
0
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US Patent 12009343 Stackable package and method
0
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US Patent 11715691 Integrated circuit package with integrated voltage regulator
0
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US Patent 11855023 Wafer level fan out semiconductor device and manufacturing method thereof
0
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US Patent 11876053 Multi-chip package and method of providing die-to-die interconnects in same
0
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US Patent 11942581 Semiconductor device with transmissive layer and manufacturing method thereof
0
Patent Primary Examiner
‌
Carl Whitehead, Jr.
Patent abstract

A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

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