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US Patent 12113026 Multi-chip package and method of providing die-to-die interconnects in same

Patent 12113026 was granted and assigned to Intel on October, 2024 by the United States Patent and Trademark Office.

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Is a

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Patent attributes

Patent Applicant

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Current Assignee

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Sujit Sharan0

Johanna M. Swan0

Aleksandar Aleksov0

Henning Braunisch0

Chia-Pin Chiu0

Hinmeng Au0

Stefanie M. Lotz0

Date of Patent

October 8, 2024

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Patent Application Number

183779910

Date Filed

October 9, 2023

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Patent Citations

US Patent 7554203 Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture

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US Patent 8064224 Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same

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US Patent 8399776 Substrate having single patterned metal layer, and package applied with the substrate , and methods of manufacturing of the substrate and package

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US Patent 8227904 Multi-chip package and method of providing die-to-die interconnects in same

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US Patent 7098542 Multi-chip configuration to connect flip-chips to flip-chips

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US Patent 7198980 Methods for assembling multiple semiconductor devices

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US Patent 7208826 Semiconductor device and method of manufacturing the same

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US Patent 7402901 Semiconductor device and method of manufacturing semiconductor device

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Patent Primary Examiner

Jami Valentine Miller

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CPC Code

H01L 2224/48227

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H01L 2224/48091

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H01L 2224/16225

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Patent abstract

A multi-chip package includes a substrate (

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