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US Patent 12080603 Active region cut process

Patent 12080603 was granted and assigned to Taiwan Semiconductor Manufacturing Company on September, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120806030
Patent Inventor Names
Kuo-Chin Liu0
You-Ting Lin0
Jiun-Ming Kuo0
Han-Yu Tsai0
Zu-Yin Liu0
Date of Patent
September 3, 2024
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Patent Application Number
174612470
Date Filed
August 30, 2021
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Patent Citations
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US Patent 10109721 Horizontal gate-all-around device having wrapped-around source and drain
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US Patent 10157799 Multi-gate device and method of fabrication thereof
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US Patent 10199502 Structure of S/D contact and method of making same
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US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
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US Patent 10290546 Threshold voltage adjustment for a gate-all-around semiconductor structure
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US Patent 9406521 Semiconductor device and method for fabricating the same
0
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US Patent 9818872 Multi-gate device and method of fabrication thereof
0
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US Patent 9887269 Multi-gate device and method of fabrication thereof
0
...
Patent Primary Examiner
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Tuan A Hoang
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CPC Code
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H01L 29/42376
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H01L 29/66795
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H01L 29/66439
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H01L 29/0673
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H01L 29/78696
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H01L 29/42392
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H01L 21/823878
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H01L 21/823481
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Patent abstract

A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.

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