US Patent 11894423 Contact resistance reduction in nanosheet device structure

Patent

US Patent 9461149 Nanowire structure with selected stack removed for reduced gate resistance and method of fabricating same

US Patent 9716143 Silicide regions in vertical gate all around (VGAA) devices and methods of forming same

US Patent 9837414 Stacked complementary FETs featuring vertically stacked horizontal nanowires

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US Patent 9881926 Static random access memory (SRAM) density scaling by using middle of line (MOL) flow

US Patent 9947804 Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

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US Patent 10236217 Stacked field-effect transistors (FETs) with shared and non-shared gates

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US Patent 10361131 Stacked field-effect transistors (FETs) with shared and non-shared gates

United States Patent and Trademark Office

Latanya N Crawford Eason

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