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US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10263100
Date of Patent
April 16, 2019
Patent Application Number
15924799
Date Filed
March 19, 2018
Patent Citations Received
‌
US Patent 12136657 Field-effect transistor and method of forming the same
0
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US Patent 11508625 Method of making a continuous channel between 3D CMOS
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US Patent 12002683 Lateral etching of silicon
0
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US Patent 12119392 Semiconductor device and method
0
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US Patent 11502079 Integrated device comprising a CMOS structure comprising well-less transistors
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US Patent 10546957 Nanosheet FET including all-around source/drain contact
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US Patent 10741456 Vertically stacked nanosheet CMOS transistor
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US Patent 10879394 Semiconductor device and method of forming the same
...
Patent Primary Examiner
‌
Nicholas J Tobergte
Patent abstract

Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.

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