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US Patent 10032867 Forming bottom isolation layer for nanosheet technology

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10032867
Date of Patent
July 24, 2018
Patent Application Number
15452188
Date Filed
March 7, 2017
Patent Citations Received
‌
US Patent 11923363 Semiconductor structure having bottom isolation and enhanced carrier mobility
3
‌
US Patent 11495688 Source and drain epitaxy and isolation for gate structures
‌
US Patent 11508807 Semiconductor device having nanosheet transistor and methods of fabrication thereof
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US Patent 11387319 Nanosheet transistor device with bottom isolation
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US Patent 11894423 Contact resistance reduction in nanosheet device structure
9
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US Patent 11489044 Nanosheet transistor bottom isolation
‌
US Patent 10361269 Forming bottom isolation layer for nanosheet technology
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US Patent 10546957 Nanosheet FET including all-around source/drain contact
...
Patent Primary Examiner
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Christine Enad
Patent abstract

A method of forming a semiconductor structure includes forming a multi-layer structure. The multi-layer structure has a substrate and two or more nanosheet layers formed above the substrate. The method also includes forming a bottom isolation layer between the substrate and the two or more nanosheet layers. The method further includes performing a fin reveal in the multi-layer structure after formation of the bottom isolation layer to form a fin. The two or more nanosheet layers provide a channel stack for a nanosheet field-effect transistor.

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