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US Patent 11855008 Stacking via structures for stress reduction

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
August 10, 2022
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Date of Patent
December 26, 2023
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Patent Application Number
17818729
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Patent Citations
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US Patent 8803306 Fan-out package structure and methods for forming the same
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US Patent 8809996 Package with passive devices and method of forming the same
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US Patent 8829676 Interconnect structure for wafer level package
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US Patent 8877554 Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
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US Patent 9000584 Packaged semiconductor device with a molding compound and a method of forming the same
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US Patent 9048222 Method of fabricating interconnect structure for package-on-package devices
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US Patent 9048233 Package systems having interposers
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US Patent 9064879 Packaging methods and structures using a die attach film
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US Patent 9111949 Methods and apparatus of wafer level package for heterogeneous integration technology
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US Patent 9263511 Package with metal-insulator-metal capacitor and method of manufacturing the same
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•••
Patent Inventor Names
Shin-Puu Jeng
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Che-Chia Yang
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Po-Yao Lin
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Chia-Hsiang Lin
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Chin-Hua Wang
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Shu-Shen Yeh
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11855008
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Patent Primary Examiner
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Selim U Ahmed
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CPC Code
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H01L 23/49822
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H01L 23/562
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H01L 21/4853
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H01L 21/4857
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H01L 21/563
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H01L 23/3185
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H01L 23/5383
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H01L 23/5386
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H01L 24/16
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H01L 2224/16227
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•••

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