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US Patent 11711928 3D memory devices and structures with control circuits

Overview Structured Data Issues Contributors

Is a

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Date Filed

February 5, 2023

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Date of Patent

July 25, 2023

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Patent Application Number

18105856

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Patent Citations

US Patent 8343851 Wafer temporary bonding method using silicon direct bonding

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US Patent 9589982 Structure and method of operation for improved gate capacity for 3D NOR flash memory

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US Patent 9595530 Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory

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US Patent 9627287 Thinning in package using separation structure as stop

1

US Patent 9673257 Vertical thin film transistors with surround gates

1

US Patent 9786677 Memory device having memory cells connected in parallel to common source and drain and method of fabrication

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US Patent 9842651 Three-dimensional vertical NOR flash thin film transistor strings

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US Patent 9997530 Three-dimensional semiconductor memory device and method of fabricating the same

1

US Patent 10199354 Die sidewall interconnects for 3D chip assemblies

1

US Patent 11251149 3D memory device and structure

1

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

1

Patent Primary Examiner

David A Zarneke

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CPC Code

H01L 2224/08145

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