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US Patent 11711928 3D memory devices and structures with control circuits
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Patent
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Date Filed
February 5, 2023
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Date of Patent
July 25, 2023
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Patent Application Number
18105856
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Patent Citations
US Patent 8343851 Wafer temporary bonding method using silicon direct bonding
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US Patent 9589982 Structure and method of operation for improved gate capacity for 3D NOR flash memory
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US Patent 9595530 Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
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US Patent 9627287 Thinning in package using separation structure as stop
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US Patent 9673257 Vertical thin film transistors with surround gates
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US Patent 9786677 Memory device having memory cells connected in parallel to common source and drain and method of fabrication
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US Patent 9842651 Three-dimensional vertical NOR flash thin film transistor strings
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US Patent 9997530 Three-dimensional semiconductor memory device and method of fabricating the same
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US Patent 10199354 Die sidewall interconnects for 3D chip assemblies
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US Patent 11251149 3D memory device and structure
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•••
Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11711928
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Patent Primary Examiner
David A Zarneke
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CPC Code
H01L 2224/08145
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H01L 25/18
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H01L 25/0657
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H01L 25/50
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H01L 23/544
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H01L 24/80
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H01L 24/08
0
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