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US Patent 9673257 Vertical thin film transistors with surround gates

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9673257
Date of Patent
June 6, 2017
Patent Application Number
15172483
Date Filed
June 3, 2016
Patent Citations Received
‌
US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12108591 Semiconductor structure, method for forming semiconductor structure and memory
0
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US Patent 12120880 3D semiconductor device and structure with logic and memory
0
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
0
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US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path
0
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US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding
0
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US Patent 11711928 3D memory devices and structures with control circuits
0
‌
US Patent 11763864 3D memory semiconductor devices and structures with bit-line pillars
...
Patent Primary Examiner
‌
Minh-Loan Tran
Patent abstract

A method is provided that includes forming a transistor by forming a first a rail gate disposed in a first direction above a substrate, forming a second rail gate disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a bridge section disposed between the first rail gate and the second rail gate.

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