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US Patent 11163120 Fiber attach enabled wafer level fanout

Patent 11163120 was granted and assigned to Ayar Labs on November, 2021 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
Ayar Labs
Ayar Labs
Date Filed
November 15, 2019
Date of Patent
November 2, 2021
Patent Applicant
Ayar Labs
Ayar Labs
Patent Application Number
20191115
Patent Citations Received
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US Patent 11694935 Systems and methods for wafer-level photonic testing
0
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US Patent 11853870 Photonic semiconductor devices and methods for manufacturing the same
0
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US Patent 12014962 Systems and methods for wafer-level photonic testing
0
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US Patent 11788929 Techniques for wafer level die testing using sacrificial structures
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11163120

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