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US Patent 11788929 Techniques for wafer level die testing using sacrificial structures

Patent 11788929 was granted and assigned to Aeva, Inc. on October, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Aeva, Inc.
Aeva, Inc.
Current Assignee
Aeva, Inc.
Aeva, Inc.
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11788929
Patent Inventor Names
Pradeep Srinivasan
Brett E. Huff
Date of Patent
October 17, 2023
Patent Application Number
17956331
Date Filed
September 29, 2022
Patent Citations
‌
US Patent 9735885 Chip-scale mid-IR scanning frequency modulated coherent ladar receiver
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US Patent 8724100 Wafer level testing of optical devices
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US Patent 8916874 Sacrificial waveguide test structures
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US Patent 9459177 Wafer-level testing of optical circuit devices
‌
US Patent 9904016 Wafer prober for testing in-wafer photonic integrated circuits
‌
US Patent 10132999 Sacrificial grating coupler for testing v-grooved integrated circuits
‌
US Patent 10190941 Silicon optical circuit for flaw detection in an optical circuit element
‌
US Patent 10222294 Wafer level testing of optical devices
...
Patent Primary Examiner
‌
Gordon J Stock, Jr.
CPC Code
‌
G01M 11/332
‌
G01M 11/333
‌
G01M 11/334
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G01M 11/335
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G01M 11/336
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G01M 11/337
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G01M 11/331
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G01M 11/338
...
Patent abstract

A method of testing a photonics die at the wafer level includes providing a sacrificial waveguide and a grating coupler at least partially in a scribe line between dies of a wafer, performing one or more tests on the dies of the wafer via the sacrificial waveguide and grating coupler in the scribe line, and removing the sacrificial waveguide during separation of the dies of the wafer.

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