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US Patent 12014962 Systems and methods for wafer-level photonic testing

Patent 12014962 was granted and assigned to Ayar Labs, Inc. on June, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Ayar Labs, Inc.
Ayar Labs, Inc.
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Current Assignee
Ayar Labs, Inc.
Ayar Labs, Inc.
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120149620
Patent Inventor Names
Forrest Sedgwick0
Alexandra Wright0
Roy Edward Meade0
Anatol Khilo0
Date of Patent
June 18, 2024
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Patent Application Number
183465550
Date Filed
July 3, 2023
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Patent Citations
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US Patent 10359567 Test systems and methods for chips in wafer scale photonic systems
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US Patent 10845555 Optical module and associated methods
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US Patent 11163120 Fiber attach enabled wafer level fanout
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US Patent 11137548 Retro reflector and associated methods
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US Patent 9459177 Wafer-level testing of optical circuit devices
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US Patent 9690042 Optical input/output device, optical electronic system including the same, and method of manufacturing the same
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US Patent 10012798 Sacrificial coupler for testing V-grooved integrated circuits
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US Patent 10145758 Wafer level optical probing structures for silicon photonics
0
...
Patent Primary Examiner
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Jerry Rahll
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Patent abstract

A semiconductor wafer includes a semiconductor chip that includes a photonic device. The semiconductor chip includes an optical fiber attachment region in which an optical fiber alignment structure is to be fabricated. The optical fiber alignment structure is not yet fabricated in the optical fiber attachment region. The semiconductor chip includes an in-plane fiber-to-chip optical coupler positioned at an edge of the optical fiber attachment region. The in-plane fiber-to-chip optical coupler is optically connected to the photonic device. A sacrificial optical structure is optically coupled to the in-plane fiber-to-chip optical coupler. The sacrificial optical structure includes an out-of-plane optical coupler configured to receive input light from a light source external to the semiconductor chip. At least a portion of the sacrificial optical structure extends through the optical fiber attachment region.

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