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US Patent 7089397 Method and system for caching attribute data for matching attributes with physical addresses

US Patent 7089404 Method and apparatus for enhancing scheduling in an advanced microprocessor

US Patent 7096460 Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation

US Patent 7098512 Layout patterns for deep well region to facilitate routing body-bias voltage

US Patent 7100061 Adaptive power control

US Patent 7108420 System for on-chip temperature measurement in integrated circuits

US Patent 7111096 Fast look-up of indirect branch destination in a dynamic translation system

US Patent 7111146 Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine

US Patent 7112978 Frequency specific closed loop feedback control of integrated circuits

US Patent 7118273 System for on-chip temperature measurement in integrated circuits

US Patent 7119580 Repeater circuit with high performance repeater mode and normal repeater mode

US Patent 7126365 System and method for measuring negative bias thermal instability with a ring oscillator

US Patent 7129771 Servo loop for well bias voltage source

US Patent 7134001 Pipeline replay support for unaligned memory operations

US Patent 7142018 Circuits and methods for detecting and assisting wire transitions

US Patent 7149851 Method and system for conservatively managing store capacity available to a processor issuing stores

US Patent 7149872 System and method for identifying TLB entries associated with a physical address of a specified range

US Patent 7151417 System and method for characterizing a potential distribution

US Patent 7173455 Repeater circuit having different operating and reset voltage ranges, and methods thereof

US Patent 7174528 Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure

US Patent 7180322 Closed loop feedback control of integrated circuits

US Patent 7203932 Method and system for using idiom recognition during a software translation process

US Patent 7205758 Systems and methods for adjusting threshold voltage

US Patent 7211478 Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions

US Patent 7212022 System and method for measuring time dependent dielectric breakdown with a ring oscillator

US Patent 7212064 Methods and systems for measuring temperature using digital signals

US Patent 7217962 Wire mesh patterns for semiconductor devices

US Patent 7221189 Dynamic node keeper system and method

US Patent 7225299 Supporting speculative modification in a data cache

US Patent 7227397 System, method and circuits for generating a signal

US Patent 7228242 Adaptive power control based on pre package characterization of integrated circuits

US Patent 7235998 System and method for measuring time dependent dielectric breakdown with a ring oscillator

US Patent 7242205 System and method for reducing heat dissipation during burn-in

US Patent 7248988 System and method for reducing temperature variation during burn in

US Patent 7249246 Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions

US Patent 7256634 Elastic pipeline latch with a safe mode

US Patent 7256639 Systems and methods for integrated circuits comprising multiple body bias domains

US Patent 7260731 Saving power when in or transitioning to a static mode of a processor

US Patent 7295041 Circuits and methods for detecting and assisting wire transitions

US Patent 7304503 Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability

US Patent 7305647 Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage

US Patent 7310008 Configurable delay chain with stacked inverter delay elements

US Patent 7310723 Methods and systems employing a flag for deferring exception handling to a commit or rollback point

US Patent 7313779 Method and system for tiling a bias design to facilitate efficient design rule checking

US Patent 7315178 System and method for measuring negative bias thermal instability with a ring oscillator

US Patent 7323367 Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions

US Patent 7329928 Voltage compensated integrated circuits

US Patent 7330054 Leakage efficient anti-glitch filter

US Patent 7330080 Ring based impedance control of an output driver

US Patent 7330959 Use of MTRR and page attribute table to support multiple byte order formats in a computer system

US Patent 7331041 Method of changing modes of code generation

US Patent 7332763 Selective coupling of voltage feeds for body bias voltage in an integrated circuit device

US Patent 7332931 Leakage efficient anti-glitch filter with variable delay stages

US Patent 7334173 Method and system for protecting processors from unauthorized debug access

US Patent 7334198 Software controlled transistor body bias

US Patent 7336090 Frequency specific closed loop feedback control of integrated circuits

US Patent 7336092 Closed loop feedback control of integrated circuits

US Patent 7336103 Stacked inverter delay chain

US Patent 7337307 Exception handling with inserted status check command accommodating floating point instruction forward move across branch

US Patent 7337439 Method for increasing the speed of speculative execution

US Patent 7343473 System and method for translating non-native instructions to native instructions for processing on a host processor

US Patent 7362165 Servo loop for well bias voltage source

US Patent 7375556 Advanced repeater utilizing signal distribution delay

US Patent 7376798 Memory management methods and systems that support cache consistency

US Patent 7380096 System and method for identifying TLB entries associated with a physical address of a specified range

US Patent 7380098 Method and system for caching attribute data for matching attributes with physical addresses

US Patent 7388260 Structure for spanning gap in body-bias voltage routing structure

US Patent 7404181 Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold

US Patent 7405597 Advanced repeater with duty cycle adjustment

US Patent 7414485 Circuits, systems and methods relating to dynamic ring oscillators

US Patent 7444471 Method and system for using external storage to amortize CPU cycle utilization

US Patent 7451300 Explicit control of speculation

US Patent 7456628 System and method for measuring negative bias thermal instability with a ring oscillator

US Patent 7463050 System and method for controlling temperature during burn-in

US Patent 7472033 Apparatus for controlling semiconductor chip characteristics

US Patent 7478226 Processing bypass directory tracking system and method

US Patent 7495466 Triple latch flip flop system and method

US Patent 7495497 Temperature compensated integrated circuits

US Patent 7496727 Secure memory access system and method

US Patent 7496868 Method and system for automated schematic diagram conversion to support semiconductor body bias designs

US Patent 7498846 Power efficient multiplexer

US Patent 7509504 Systems and methods for control of integrated circuits comprising body biasing systems

US Patent 7562233 Adaptive control of operating and body bias voltages