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US Patent 9761308 Systems and methods for adaptive read level adjustment

Patent 9761308 was granted and assigned to Western Digital on September, 2017 by the United States Patent and Trademark Office.

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Patent attributes

Current Assignee

Western Digital

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Aldo G. Cometti1

Date of Patent

September 12, 2017

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Patent Application Number

150684271

Date Filed

March 11, 2016

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Patent Citations Received

US Patent 11934666 Memory device with dynamic program-verify voltage calibration

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US Patent 12073890 Memory system

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US Patent 12001286 Memory device with dynamic processing level calibration

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US Patent 11714580 Dynamic background scan optimization in a memory sub-system

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US Patent 11714709 Enhanced block management for a memory subsystem

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US Patent 11953980 Memory sub-system with dynamic calibration using component-based function(s)

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Patent Primary Examiner

1

Patent abstract

Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.

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