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US Patent 11953980 Memory sub-system with dynamic calibration using component-based function(s)

Patent 11953980 was granted and assigned to Micron Technology on April, 2024 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
Micron Technology
Micron Technology
1
Current Assignee
Micron Technology
Micron Technology
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
119539801
Patent Inventor Names
Bruce A. Liikanen1
Violante Moschiano1
Gerald L. Cadloni1
Date of Patent
April 9, 2024
1
Patent Application Number
180734021
Date Filed
December 1, 2022
1
Patent Citations
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US Patent 9092350 Detection and handling of unbalanced errors in interleaved codewords
1
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US Patent 7437498 Method and system for optimizing reliability and performance of programming data in non-volatile memory devices
1
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US Patent 8006166 Programming error correction code into a solid state memory device with varying bits per cell
1
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US Patent 8112064 Function lock information notification method and mobile communication terminal
1
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US Patent 10566063 Memory system with dynamic calibration using a trim management mechanism
1
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US Patent 10664194 Memory system with dynamic calibration using a variable adjustment mechanism
1
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US Patent 10877827 Read voltage optimization
1
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US Patent 10936205 Techniques for retention and read-disturb aware health binning
1
...
Patent Primary Examiner
‌
Joshua P Lottich
1
CPC Code
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G11C 16/26
1
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G06F 11/079
1
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G06F 11/0751
1
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G06F 11/073
1
Patent abstract

An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. The multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.

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