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US Patent 8710676 Stacked structure and stacked method for three-dimensional chip

Patent 8710676 was granted and assigned to Industrial Technology Research Institute on April, 2014 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 11854785 Package structure for heat dissipation
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Patent abstract

A stacked structure and a stacked method for a three-dimensional integrated circuit are provided. The provided stacked method includes separating a logic chip into a function chip and an I/O chip; stacking the function chip above the I/O chip; and stacking at least one memory chip between the function chip and the I/O chip.

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Patent Inventor Names
Ding-Ming Kwai0
Yung-Fa Chou0
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US Patent 08710676 Stacked structure and stacked method for three-dimensional chip US Patent 8710676 Stacked structure and stacked method for three-dimensional chip

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Patent Number
087106760
Patent Number
87106760
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087106760
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Infobox
Is a
Patent
Patent
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Current Assignee
Industrial Technology Research Institute
Industrial Technology Research Institute
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
087106760
Date of Patent
April 29, 2014
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Patent Application Number
129861840
Date Filed
January 7, 2011
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=087106760
Patent Primary Examiner
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Peniel M Gumedzoe
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=08710676
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 US Patent 08710676 Stacked structure and stacked method for three-dimensional chip

Infobox
Is a
Patent
Patent
Current assignee
Industrial Technology Research Institute
Industrial Technology Research Institute
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
08710676
Date of patent
April 29, 2014
Patent application number
12986184
Date Filed
January 7, 2011
Patent primary examiner
‌
Peniel M Gumedzoe

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