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US Patent 8158515 Method of making 3D integrated circuits

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
February 1, 2010
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Date of Patent
April 17, 2012
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Patent Application Number
12697562
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Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12068187 3D semiconductor device and structure with bonding and DRAM memory cells
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US Patent 12080743 Multilevel semiconductor device and structure with image sensors and wafer bonding
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US Patent 12094829 3D semiconductor device and structure
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US Patent 12094892 3D micro display device and structure
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
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US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding
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US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path
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•••
Patent Inventor Names
Steven J. Koester
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Mukta G. Farooq
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Subramanian S. Iyer
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Huilong Zhu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8158515
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Patent Primary Examiner
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Tammy Thanh Nguyen
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