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US Patent 8026521 Semiconductor device and structure

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
October 11, 2010
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Date of Patent
September 27, 2011
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Patent Application Number
12901890
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Patent Citations Received
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US Patent 12105650 Quasi-volatile system-level memory
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US Patent 11937424 Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same
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US Patent 12002523 Memory circuit, system and method for rapid retrieval of data sets
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US Patent 12068286 Device with embedded high-bandwidth, high-capacity memory using wafer bonding
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 11705496 Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array
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US Patent 11710729 Wafer bonding in fabrication of 3-dimensional NOR memory circuits
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US Patent 11749344 Three-dimensional vertical nor flash thin-film transistor strings
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US Patent 11751388 3-dimensional nor strings with segmented shared source regions
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US Patent 11751391 Methods for fabricating a 3-dimensional memory structure of nor memory strings
•••
Patent Inventor Names
Deepak C. Sekar
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Zvi Or-Bach
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
8026521
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Patent Primary Examiner
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Brook Kebede
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