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US Patent 12068286 Device with embedded high-bandwidth, high-capacity memory using wafer bonding

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120682860
Patent Inventor Names
Khandker Nazrul Quader0
Frank Sai-keung Lee0
Sayeef Salahuddin0
Scott Brad Herner0
Robert Norman0
Eli Harari0
Siu Lung Chan0
Mehrdad Mofidi0
...
Date of Patent
August 20, 2024
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Patent Application Number
181382700
Date Filed
April 24, 2023
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Patent Citations
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US Patent 8542513 Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells
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US Patent 10217719 Semiconductor device assemblies with molded support substrates
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US Patent 10249370 Three-dimensional vertical NOR flash thing-film transistor strings
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US Patent 10254968 Hybrid memory device for lookup operations
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US Patent 10283452 Three-dimensional memory devices having a plurality of NAND strings
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US Patent 10283493 Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof
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US Patent 10297578 Memory device
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US Patent 10319696 Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages
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Patent Primary Examiner
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Mamadou L Diallo
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CPC Code
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G11C 16/0483
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G06N 3/02
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G06F 2212/72
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G06F 2212/60
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G06F 12/0802
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G06F 11/1068
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G06F 3/0655
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G06F 3/0604
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Patent abstract

An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

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