US Patent 11710729 Wafer bonding in fabrication of 3-dimensional NOR memory circuits

A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.