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US Patent 7768115 Stack chip and stack chip package having the same

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
77681151
Patent Inventor Names
Dong-Ho Lee1
Jong-Joo Lee1
Date of Patent
August 3, 2010
1
Patent Application Number
122673431
Date Filed
November 7, 2008
1
Patent Citations Received
‌
US Patent 12136562 3D semiconductor device and structure with single-crystal layers
2
‌
US Patent 12094829 3D semiconductor device and structure
3
‌
US Patent 12094892 3D micro display device and structure
4
‌
US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
5
‌
US Patent 12120880 3D semiconductor device and structure with logic and memory
6
‌
US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
7
‌
US Patent 11694922 Multilevel semiconductor device and structure with oxide bonding
8
‌
US Patent 11694944 3D semiconductor device and structure with metal layers and a connective path
9
...
Patent Primary Examiner
‌
Jasmine J Clark
1
Patent abstract

Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

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