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US Patent 7632738 Wafer bonding method

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
December 29, 2008
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Date of Patent
December 15, 2009
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Patent Application Number
12345503
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Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
0
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US Patent 11711928 3D memory devices and structures with control circuits
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US Patent 11763864 3D memory semiconductor devices and structures with bit-line pillars
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US Patent 11784082 3D semiconductor device and structure with bonding
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US Patent 11784169 3D semiconductor device and structure with metal layers
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US Patent 11804396 Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
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US Patent 11854857 Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
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•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
7632738
0
Patent Primary Examiner
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Thao P. Le
0

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