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US Patent 7224184 High bandwidth reconfigurable on-chip network for reconfigurable systems

Patent 7224184 was granted and assigned to Xilinx on May, 2007 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Current Assignee
Xilinx
Xilinx
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
72241840
Patent Inventor Names
Delon Levi0
Tobias J. Becker0
Date of Patent
May 29, 2007
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Patent Application Number
109819320
Date Filed
November 5, 2004
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Patent Citations Received
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US Patent 11693808 Multi-die integrated circuit with data processing engine array
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US Patent 11853235 Communicating between data processing engines using shared memory
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US Patent 11922223 Flexible data-driven software control of reconfigurable platforms
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US Patent 12001367 Multi-die integrated circuit with data processing engine array
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US Patent 11972132 Data processing engine arrangement in a device
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US Patent 12026444 Dynamic port handling for isolated modules and dynamic function exchange
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US Patent 12105667 Device with data processing engine array that enables partial reconfiguration
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US Patent 12079158 Reconfigurable neural engine with extensible instruction set architecture
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...
Patent Primary Examiner
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Anh Q Tran
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Patent abstract

A crossbar switch (50) is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules (40), the crossbar switch (50) providing communication links between the modules (40). The modules (40) and crossbar switch (50) can be easily updated in a partial reconfiguration process changing only portions of modules (40) and the crossbar switch (50) while other portions remain active. The crossbar switch (50) uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch (50) can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.

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