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US Patent 11853235 Communicating between data processing engines using shared memory

Patent 11853235 was granted and assigned to Xilinx Inc on December, 2023 by the United States Patent and Trademark Office.

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Contents

Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
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Xilinx Inc
1
Current Assignee
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Xilinx Inc
1
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
118532351
Patent Inventor Names
Jan Langer1
Juan J. Noguera Serra1
Goran Hk Bilski1
Baris Ozgul1
Date of Patent
December 26, 2023
1
Patent Application Number
178260681
Date Filed
May 26, 2022
1
Patent Citations
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US Patent 7302625 Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
1
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US Patent 6907595 Partial reconfiguration of a programmable logic device using an on-chip processor
1
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US Patent 7024651 Partial reconfiguration of a programmable gate array using a bus macro
1
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US Patent 7057413 Large crossbar switch implemented in FPGA
1
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US Patent 7124338 Methods of testing interconnect lines in programmable logic devices using partial reconfiguration
1
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US Patent 7224184 High bandwidth reconfigurable on-chip network for reconfigurable systems
1
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US Patent 8359448 Specific memory controller implemented using reconfiguration
1
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US Patent 8415974 Methods and circuits enabling dynamic reconfiguration
1
...
Patent Primary Examiner
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Kalpit Parikh
1
CPC Code
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G06F 12/084
1
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G06F 13/1663
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G11C 8/16
1
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G06F 15/167
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G06F 9/544
1
Patent abstract

Examples herein describe techniques for transferring data between data processing engines in an array using shared memory. In one embodiment, certain engines in the array have connections to the memory in neighboring engines. For example, each engine may have its own assigned memory module which can be accessed directly (e.g., without using a streaming or memory mapped interconnect). In addition, the surrounding engines (referred to herein as the neighboring engines) may also include direct connections to the memory module. Using these direct connections, the cores can load and/or store data in the neighboring memory modules.

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