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US Patent 12001367 Multi-die integrated circuit with data processing engine array

Patent 12001367 was granted and assigned to Xilinx Inc on June, 2024 by the United States Patent and Trademark Office.

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Contents

Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent
1

Patent attributes

Patent Applicant
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Xilinx Inc
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Current Assignee
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Xilinx Inc
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120013671
Patent Inventor Names
Juan J. Noguera Serra1
Tim Tuan1
Sridhar Subramanian1
Date of Patent
June 4, 2024
1
Patent Application Number
183201471
Date Filed
May 18, 2023
1
Patent Citations
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US Patent 7302625 Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
1
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US Patent 7394288 Transferring data in a parallel processing environment
1
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US Patent 7477072 Circuit for and method of enabling partial reconfiguration of a device having programmable logic
1
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US Patent 7478357 Versatile bus interface macro for dynamically reconfigurable designs
1
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US Patent 7482836 High bandwidth reconfigurable on-chip network for reconfigurable systems
1
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US Patent 7509617 Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
1
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US Patent 7518396 Apparatus and method for reconfiguring a programmable logic device
1
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US Patent 7546572 Shared memory interface in a programmable logic device using partial reconfiguration
1
...
Patent Primary Examiner
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Michael Sun
1
Patent abstract

An integrated circuit includes an interposer and a die coupled to the interposer. The die includes a first data processing engine (DPE) array and a second DPE array. The first DPE array includes a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs. The second DPE array includes a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs. The integrated circuit includes one or more other dies having a first die interface coupled to, and configured to communicate with, the first DPE interface via the interposer and a second die interface coupled to, and configured to communicate with, the second DPE interface via the interposer.

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