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US Patent 6967149 Storage structure with cleaved layer

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 20, 2003
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Date of Patent
November 22, 2005
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Patent Application Number
10718137
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Patent Citations Received
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US Patent 12136562 3D semiconductor device and structure with single-crystal layers
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US Patent 12068187 3D semiconductor device and structure with bonding and DRAM memory cells
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US Patent 12080743 Multilevel semiconductor device and structure with image sensors and wafer bonding
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US Patent 12094829 3D semiconductor device and structure
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US Patent 12094965 3D semiconductor device and structure with metal layers and memory cells
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US Patent 12094892 3D micro display device and structure
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US Patent 12120880 3D semiconductor device and structure with logic and memory
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US Patent 12125737 3D semiconductor device and structure with metal layers and memory cells
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US Patent 11854857 Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
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US Patent 11855100 Multilevel semiconductor device and structure with oxide bonding
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•••
Patent Inventor Names
Andrew L. Van Brocklin
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Kenneth James Eldredge
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Neal W. Meyer
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Peter Fricke
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Warren Jackson
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
6967149
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Patent Primary Examiner
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Mary Wilczewski
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