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US Patent 12062721 Latch-up prevention

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
0
Date Filed
February 7, 2022
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Date of Patent
August 13, 2024
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Patent Application Number
17666240
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Patent Citations
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US Patent 10325820 Source and drain isolation for CMOS nanosheet with one block mask
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US Patent 10475902 Spacers for nanowire-based integrated circuit device and method of fabricating same
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US Patent 11245036 Latch-up prevention
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US Patent 10109721 Horizontal gate-all-around device having wrapped-around source and drain
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US Patent 10157799 Multi-gate device and method of fabrication thereof
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US Patent 10199502 Structure of S/D contact and method of making same
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US Patent 10290546 Threshold voltage adjustment for a gate-all-around semiconductor structure
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US Patent 9818872 Multi-gate device and method of fabrication thereof
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US Patent 9887269 Multi-gate device and method of fabrication thereof
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US Patent 9899398 Non-volatile memory device having nanocrystal floating gate and method of fabricating same
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•••
Patent Inventor Names
Kuo-Cheng Chiang
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Zhi-Chang Lin
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Shih-Cheng Chen
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12062721
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Patent Primary Examiner
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Tong-Ho Kim
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CPC Code
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H01L 29/7831
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H01L 27/088
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H01L 27/0886
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H01L 29/0649
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B82Y 10/00
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H01L 29/785
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H01L 29/78612
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H01L 21/02236
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H01L 21/02532
0
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H01L 21/02603
0
•••

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