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US Patent 11996356 Low-stress passivation layer

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
June 5, 2023
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Date of Patent
May 28, 2024
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Patent Application Number
18329327
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Patent Citations
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US Patent 8022544 Chip structure
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US Patent 8242601 Semiconductor chip with passivation layer comprising metal interconnect and contact pads
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US Patent 8581404 Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
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US Patent 9000584 Packaged semiconductor device with a molding compound and a method of forming the same
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US Patent 9048222 Method of fabricating interconnect structure for package-on-package devices
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US Patent 9048233 Package systems having interposers
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US Patent 9064879 Packaging methods and structures using a die attach film
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US Patent 9111949 Methods and apparatus of wafer level package for heterogeneous integration technology
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US Patent 9263511 Package with metal-insulator-metal capacitor and method of manufacturing the same
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US Patent 9281254 Methods of forming integrated circuit package
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•••
Patent Inventor Names
Hsiang-Ku Shen
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Chun-Li Lin
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Dian-Hau Chen
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11996356
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Patent Primary Examiner
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Nitin Parekh
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CPC Code
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H01L 23/53295
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H01L 23/5384
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H01L 23/5226
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