Log in
Sign up
Golden has been acquired by ComplyAdvantage.Read about it here ⟶
‌

US Patent 11769053 Apparatuses and methods for operating neural networks

Patent 11769053 was granted and assigned to Micron Technology on September, 2023 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity

All edits

Edits on 27 Sep, 2023
"Created via: Entity Importer"
Golden AI profile picture
Golden AI
created this topic on 27 Sep, 2023
Edits made to:
Infobox (+81 properties)
Article (+490 characters)
‌

 US Patent 11769053 Apparatuses and methods for operating neural networks

Article

Patent abstract

The present disclosure includes apparatuses and methods for operating neural networks. An example apparatus includes a plurality of neural networks, wherein the plurality of neural networks are configured to receive a particular portion of data and wherein each of the plurality of neural networks are configured to operate on the particular portion of data during a particular time period to make a determination regarding a characteristic of the particular portion of data.

Infobox
Is a
Patent
Patent
Patent Applicant
Micron Technology
Micron Technology
Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11769053
Patent Inventor Names
Perry V. Lea
Date of Patent
September 26, 2023
Patent Application Number
17543498
Date Filed
December 6, 2021
Patent Citations
‌
US Patent 7173857 Nonvolatile semiconductor memory device capable of uniformly inputting/outputting data
‌
US Patent 7187585 Read operation for non-volatile storage that includes compensation for coupling
‌
US Patent 7196928 Compensating for coupling during read operations of non-volatile memory
‌
US Patent 7260565 Method and apparatus for high speed table search
‌
US Patent 7260672 Using data stored in a destructive-read memory
‌
US Patent 7372715 Architecture and method for NAND flash memory
‌
US Patent 7400532 Programming method to reduce gate coupling interference for non-volatile memory
‌
US Patent 7406494 Method of generating a cycle-efficient bit-reverse index array for a wireless communication system
‌
US Patent 7447720 Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements
‌
US Patent 7454451 Method for finding local extrema of a set of values for a parallel processing element
‌
US Patent 7457181 Memory device and method of operating the same
‌
US Patent 7535769 Time-dependent compensation currents in non-volatile memory read operations
‌
US Patent 7546438 Algorithm mapping, specialized instructions and architecture features for smart memory computing
‌
US Patent 7562198 Semiconductor device and semiconductor signal processing apparatus
‌
US Patent 7574466 Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements
‌
US Patent 7602647 System that compensates for coupling based on sensing a neighbor using coupling
‌
US Patent 7663928 Sense amplifier circuit having current mirror architecture
‌
US Patent 7685365 Transactional memory execution utilizing virtual memory
‌
US Patent 7692466 Sense amplifier based flip-flop
‌
US Patent 7752417 Dynamic selection of memory virtualization techniques
‌
US Patent 7791962 Semiconductor device and semiconductor signal processing apparatus
‌
US Patent 7796453 Semiconductor device
‌
US Patent 7805587 Memory addressing controlled by PTE fields
‌
US Patent 7808854 Systems and methods for data transfers between memory cells
‌
US Patent 7827372 Intergrated circuit and a method of cache remapping
‌
US Patent 7869273 Reducing the impact of interference during programming
‌
US Patent 7898864 Read operation for memory with compensation for coupling based on write-erase cycles
‌
US Patent 7924628 Operation of a non-volatile memory array
‌
US Patent 7937535 Managing cache coherency in a data processing apparatus
‌
US Patent 7957206 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
‌
US Patent 7979667 Memory array search engine
‌
US Patent 7996749 Signal loss detector for high-speed serial interface of a programmable logic device
‌
US Patent 8042082 Three dimensional memory in a system on a chip
‌
US Patent 8045391 Non-volatile memory and method with improved sensing having bit-line lockout control
‌
US Patent 8059438 Content addressable memory array programmed to perform logic operations
‌
US Patent 8095825 Error correction method with instruction level rollback
‌
US Patent 8117462 Delivery point validation system
‌
US Patent 8164942 High performance eDRAM sense amplifier
‌
US Patent 8208328 Semiconductor memory device
‌
US Patent 8213248 Semiconductor memory device having improved local input/output line precharge scheme
‌
US Patent 8223568 Semiconductor memory device adopting improved local input/output line precharging scheme
‌
US Patent 8238173 Using storage cells to perform computation
‌
US Patent 8274841 Semiconductor signal processing device
‌
US Patent 8279683 Digit line comparison circuits
‌
US Patent 8310884 Semiconductor memory device
‌
US Patent 8332367 Parallel data redundancy removal
‌
US Patent 8339824 Nearest neighbor serial content addressable memory
‌
US Patent 8339883 Semiconductor memory device
‌
US Patent 8347154 Use of hashing function to distinguish random and repeat errors in a memory system
‌
US Patent 8351292 Semiconductor device and data processing system
‌
US Patent 8356144 Vector processor system
‌
US Patent 8417921 Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector
‌
US Patent 8462532 Fast quaternary content addressable memory cell
‌
US Patent 8484276 Processing array data on SIMD multi-core processor architectures
‌
US Patent 8495438 Technique for memory imprint reliability improvement
‌
US Patent 8503250 High speed DRAM architecture with uniform access latency
‌
US Patent 8526239 Semiconductor memory device and method of operating the same
‌
US Patent 8533245 Multipliers with a reduced number of memory blocks
‌
US Patent 8555037 Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture
‌
US Patent 8599613 Nonvolatile semiconductor memory
‌
US Patent 8605015 Spatial light modulator with masking-comparators
‌
US Patent 8625376 Semiconductor memory device and method of operation the same
‌
US Patent 8644101 Local sense amplifier circuit and semiconductor memory device including the same
‌
US Patent 8650232 System and method for determination of a horizontal minimum of digital values
‌
US Patent 8873272 Semiconductor memory apparatus and test circuit therefor
‌
US Patent 8964496 Apparatuses and methods for performing compare operations using sensing circuitry
‌
US Patent 8971124 Apparatuses and methods for performing logical operations using sensing circuitry
‌
US Patent 9015390 Active memory data compression system and method
‌
US Patent 9047193 Processor-cache system and method
‌
US Patent 9165023 Integrated circuit device and method for determining an index of an extreme value within an array of values
‌
US Patent 9317785 Method and system for determining ethnicity category of facial images based on multi-level primary and auxiliary classifiers
Patent Primary Examiner
‌
Daniel C Puentes

Find more entities like US Patent 11769053 Apparatuses and methods for operating neural networks

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo
By using this site, you agree to our Terms of Service.