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US Patent 11387319 Nanosheet transistor device with bottom isolation
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Patent
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Date Filed
September 11, 2019
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Date of Patent
July 12, 2022
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Patent Application Number
16567767
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Patent Citations
US Patent 10243054 Integrating standard-gate and extended-gate nanosheet transistors on the same substrate
US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
US Patent 10615257 Patterning method for nanosheet transistors
US Patent 10840329 Nanosheet transistor having improved bottom isolation
US Patent 11069819 Field-effect transistors with channel regions that include a two-dimensional material on a mandrel
US Patent 10332803 Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming
US Patent 10032867 Forming bottom isolation layer for nanosheet technology
US Patent 10134901 Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures
US Patent 10141403 Integrating thin and thick gate dielectric nanosheet transistors on same chip
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Patent Inventor Names
Pietro Montanini
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Andrew M. Greene
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Ruilong Xie
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Veeraraghavan S. Basker
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11387319
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Patent Primary Examiner
Mary A Wilczweski
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CPC Code
H01L 29/78696
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H01L 27/0924
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H01L 29/775
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H01L 29/1079
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H01L 29/78687
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H01L 29/0673
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H01L 21/84
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H01L 27/1203
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H01L 29/7827
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H01L 29/66666
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