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US Patent 11282961 Enhanced bottom dielectric isolation in gate-all-around devices

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Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
112829611
Patent Inventor Names
Ruilong Xie1
Andrew Greene1
Julien Frougier1
Kangguo Cheng1
Date of Patent
March 22, 2022
1
Patent Application Number
168281621
Date Filed
March 24, 2020
1
Patent Citations
‌
US Patent 10453824 Structure and method to form nanosheet devices with bottom isolation
‌
US Patent 10256158 Insulated epitaxial structures in nanosheet complementary field effect transistors
‌
US Patent 10720431 Methods of fabricating semiconductor devices having gate-all-around structure with oxygen blocking layers
‌
US Patent 10032867 Forming bottom isolation layer for nanosheet technology
‌
US Patent 10170638 Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer
Patent Primary Examiner
‌
Changhyun Yi
1
CPC Code
‌
H01L 2029/7858
1
‌
H01L 29/785
1

A gate-all-around (GAA) semiconductor device structure and method for forming the same. The GAA structure includes a nanosheet stack disposed over a patterned portion of a substrate, and an encapsulation structure surrounding the patterned portion of the substrate underlying the nanosheet stack. The method for forming the GAA structure includes forming a liner over and in contact with a nanosheet fin, a sacrificial layer disposed below the nanosheet fin, and a patterned portion of a substrate underlying the nanosheet fin. At least one portion of the liner is etched down to the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the nanosheet fin and the patterned portion of the substrate. An insulting layer is formed within the cavity, where the patterned portion of the substrate within one or more gate regions is encapsulated by the insulting layer and the liner.

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