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US Patent 11011643 Nanosheet FET including encapsulated all-around source/drain contact

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 5, 2019
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Date of Patent
May 18, 2021
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Patent Application Number
16674090
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Patent Citations
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US Patent 10243054 Integrating standard-gate and extended-gate nanosheet transistors on the same substrate
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US Patent 10249541 Forming a hybrid channel nanosheet semiconductor structure
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US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
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US Patent 10325820 Source and drain isolation for CMOS nanosheet with one block mask
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US Patent 10276442 Wrap-around contacts formed with multiple silicide layers
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US Patent 10483166 Vertically stacked transistors
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US Patent 10002939 Nanosheet transistors having thin and thick gate dielectric material
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US Patent 10032867 Forming bottom isolation layer for nanosheet technology
Patent Citations Received
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US Patent 12132118 Semiconductor device having a multilayer source/drain region and methods of manufacture
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Patent Inventor Names
Chen Zhang
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Chun Wing Yeung
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Peng Xu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11011643
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Patent Primary Examiner
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Alexander O Williams
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