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US Patent 10483166 Vertically stacked transistors

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
June 26, 2018
Date of Patent
November 19, 2019
Patent Application Number
16018710
Patent Citations
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US Patent 10192867 Complementary FETs with wrap around contacts and method of forming same
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US Patent 10236217 Stacked field-effect transistors (FETs) with shared and non-shared gates
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US Patent 10096607 Three-dimensional stacked junctionless channels for dense SRAM
Patent Citations Received
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US Patent 11916073 Stacked complementary field effect transistors
0
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US Patent 11837604 Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
0
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US Patent 11869812 Stacked complementary field effect transistors
0
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US Patent 11495688 Source and drain epitaxy and isolation for gate structures
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US Patent 11538814 Static random access memory of 3D stacked devices
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US Patent 10930563 Formation of stacked nanosheet semiconductor devices
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US Patent 11011643 Nanosheet FET including encapsulated all-around source/drain contact
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10483166
Patent Primary Examiner
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Allan R. Wilson

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