US Patent 10930563 Formation of stacked nanosheet semiconductor devices

A method for fabricating a stacked nanosheet semiconductor device includes forming nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate. The method includes patterning a gate structure on the nanosheet stacks and forming a source and drain on the stacks. The method further includes growing a first epitaxial layer on the source and drain. The method includes etching an interlayer dielectric on the first epitaxial layer. The method includes etching a portion of the first epitaxial layer forming a channel and growing a second epitaxial layer and etching a portion of the interlayer etching a portion of the first liner, forming a pFET. The method includes forming an nFET. The method includes the pFET and the nFET being disposed adjacent to one another vertically and a drain of the pFET and a drain of the nFET being electrically connected.