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US Patent 10043967 Self-compensation of stray field of perpendicular magnetic elements

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Patent abstract

A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
100439670
Date of Patent
August 7, 2018
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Patent Application Number
144545090
Date Filed
August 7, 2014
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Patent Citations Received
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US Patent 10347314 Method and apparatus for bipolar memory write-verify
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US Patent 10360962 Memory array with individually trimmable sense amplifiers
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US Patent 10360964 Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device
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US Patent 10366774 Device with dynamic redundancy registers
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US Patent 10366775 Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation
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US Patent 10395711 Perpendicular source and bit lines for an MRAM array
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US Patent 10395712 Memory array with horizontal source line and sacrificial bitline per virtual source
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US Patent 10411185 Process for creating a high density magnetic tunnel junction array test platform
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US Patent 10424393 Method of reading data from a memory device using multiple levels of dynamic redundancy registers
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US Patent 10446744 Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same
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US Patent 10437491 Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register
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US Patent 10437723 Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device
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US Patent 10481976 Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers
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US Patent 10489245 Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them
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US Patent 10529439 On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects
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US Patent 10529915 Bit line structures for three-dimensional arrays with magnetic tunnel junction devices including an annular free magnetic layer and a planar reference magnetic layer
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US Patent 10546624 Multi-port random access memory
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US Patent 10546625 Method of optimizing write voltage based on error buffer occupancy
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US Patent 10593396 Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
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US Patent 10600478 Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations
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US Patent 10615337 Process for creating a high density magnetic tunnel junction array test platform
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US Patent 10650875 System for a wide temperature range nonvolatile memory
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US Patent 10656994 Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques
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US Patent 10784437 Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer
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US Patent 10811594 Process for hard mask development for MRAM pillar formation using photolithography
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US Patent 10818331 Multi-chip module for MRAM devices with levels of dynamic redundancy registers
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US Patent 10840439 Magnetic tunnel junction (MTJ) fabrication methods and systems
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US Patent 10886330 Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch
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US Patent 10891997 Memory array with horizontal source line and a virtual source line
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US Patent 10930332 Memory array with individually trimmable sense amplifiers
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US Patent 10971680 Multi terminal device stack formation methods
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US Patent 11380838 Magnetic memory devices with layered electrodes and methods of fabrication
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US Patent 11621293 Multi terminal device stack systems and methods
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Patent Primary Examiner
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Meiya Li
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Patent Citations Received
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US Patent 11621293 Multi terminal device stack systems and methods
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