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US Patent 10019668 Scheduling neural network processing

Patent 10019668 was granted and assigned to Google on July, 2018 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Google
Google
Current Assignee
Google
Google
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10019668
Date of Patent
July 10, 2018
Patent Application Number
15599559
Date Filed
May 19, 2017
Patent Citations Received
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US Patent 12131182 Convolutional neural network operation grouping based on memory unit capacity
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US Patent 11461579 Configurable neural network engine for convolutional filter sizes
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US Patent 11475306 Processing for multiple input data sets
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US Patent 11494582 Configurable neural network engine of tensor arrays and memory cells
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US Patent 11494620 Systolic neural network engine capable of backpropagation
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US Patent 11915139 Modifying machine learning models to improve locality
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US Patent 12067492 Processing for multiple input data sets in a multi-layer neural network
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US Patent 11461631 Scheduling neural network computations based on memory capacity
...
Patent Primary Examiner
‌
Alexey Shmatov
Patent abstract

A computer-implemented method includes receiving a batch of neural network inputs to be processed using a neural network on a hardware circuit. The neural network has multiple layers arranged in a directed graph and each layer has a respective set of parameters. The method includes determining a partitioning of the neural network layers into a sequence of superlayers. Each superlayer is a partition of the directed graph that includes one or more layers. The method includes processing the batch of inputs using the hardware circuit, which includes, for each superlayer in the sequence: i) loading the respective set of parameters for the layers in the superlayer into memory of the hardware circuit, and ii) for each input in the batch, processing the input through each of the layers in the superlayer using the parameters in the memory of the hardware circuit to generate a superlayer output for the input.

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