List of VIA Technologies patents

Patents where

Current Assignee

Name

VIA Technologies

Name	Description	Patent Applicant	Current Assignee	Patent Jurisdiction	Patent Number	Date of Patent
‌ US Patent 7196731 Method and apparatus of adaptive de-interlacing of dynamic image	Patent 7196731 was granted and assigned to VIA Technologies on March, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7196731	March 27, 2007
‌ US Patent 7376686 Apparatus and method for generating packed sum of absolute differences	Patent 7376686 was granted and assigned to VIA Technologies on May, 2008 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7376686	May 20, 2008
‌ US Patent 6873927 Control method of an automatic integrated circuit full testing system	Patent 6873927 was granted and assigned to VIA Technologies on March, 2005 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	6873927	March 29, 2005
‌ US Patent 7191320 Apparatus and method for performing a detached load operation in a pipeline microprocessor	Patent 7191320 was granted and assigned to VIA Technologies on March, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7191320	March 13, 2007
‌ US Patent 7107438 Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions	Patent 7107438 was granted and assigned to VIA Technologies on September, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7107438	September 12, 2006
‌ US Patent 12118743 Electronic apparatus and object detection method	Patent 12118743 was granted and assigned to VIA Technologies on October, 2024 by the United States Patent and Trademark Office.	VIA Technologies	VIA Technologies	United States Patent and Trademark Office	12118743	October 15, 2024
‌ US Patent 6914424 Automatic integrated circuit testing system and device using an integrative computer and method for the same	Patent 6914424 was granted and assigned to VIA Technologies on July, 2005 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	6914424	July 5, 2005
‌ US Patent 6977348 High density laminated substrate structure and manufacture method thereof	Patent 6977348 was granted and assigned to VIA Technologies on December, 2005 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	6977348	December 20, 2005
‌ US Patent 7206026 Method and apparatus for adaptive frame rate conversion	Patent 7206026 was granted and assigned to VIA Technologies on April, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7206026	April 17, 2007
‌ US Patent 7154499 Two-level rejection in 3D graphics	Patent 7154499 was granted and assigned to VIA Technologies on December, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7154499	December 26, 2006
‌ US Patent 6951773 Chip packaging structure and manufacturing process thereof	Patent 6951773 was granted and assigned to VIA Technologies on October, 2005 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	6951773	October 4, 2005
‌ US Patent 7313658 Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests	Patent 7313658 was granted and assigned to VIA Technologies on December, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7313658	December 25, 2007
‌ US Patent 6914509 Transformer former between two layout layers	Patent 6914509 was granted and assigned to VIA Technologies on July, 2005 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	6914509	July 5, 2005
‌ US Patent 7114022 Method for generating interrupt signal and media access controller utilizing the same	Patent 7114022 was granted and assigned to VIA Technologies on September, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7114022	September 26, 2006
‌ US Patent 7148888 Head/data request in 3D graphics	Patent 7148888 was granted and assigned to VIA Technologies on December, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7148888	December 12, 2006
‌ US Patent 7088359 Vertex reordering in 3D graphics	Patent 7088359 was granted and assigned to VIA Technologies on August, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7088359	August 8, 2006
‌ US Patent 7305027 Receiver and the compensation method therefor	Patent 7305027 was granted and assigned to VIA Technologies on December, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7305027	December 4, 2007
‌ US Patent 11500801 Computing apparatus utilizing programmable logic circuit to implement direct memory access engine and at least one physical engine and providing data to be processed to at least one physical engine through direct memory access engine	Patent 11500801 was granted and assigned to VIA Technologies on November, 2022 by the United States Patent and Trademark Office.	VIA Technologies	VIA Technologies	United States Patent and Trademark Office	11500801	November 15, 2022
‌ US Patent 7158143 Fast algorithm for anisotropic texture sampling	Patent 7158143 was granted and assigned to VIA Technologies on January, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7158143	January 2, 2007
‌ US Patent 7000073 Buffer controller and management method thereof	Patent 7000073 was granted and assigned to VIA Technologies on February, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7000073	February 14, 2006
‌ US Patent 7082489 Data memory controller that supports data bus invert	Patent 7082489 was granted and assigned to VIA Technologies on July, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7082489	July 25, 2006
‌ US Patent 7176559 Integrated circuit package with a balanced-part structure	Patent 7176559 was granted and assigned to VIA Technologies on February, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7176559	February 13, 2007
‌ US Patent 7206028 Method and apparatus of adaptive de-interlacing of dynamic image	Patent 7206028 was granted and assigned to VIA Technologies on April, 2007 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7206028	April 17, 2007
‌ US Patent 7480685 Apparatus and method for generating packed sum of absolute differences	Patent 7480685 was granted and assigned to VIA Technologies on January, 2009 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7480685	January 20, 2009
‌ US Patent 7149992 Method for faster timing closure and better quality of results in IC physical design	Patent 7149992 was granted and assigned to VIA Technologies on December, 2006 by the United States Patent and Trademark Office.		VIA Technologies	United States Patent and Trademark Office	7149992	December 12, 2006

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