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List of MEARS Technologies patents

List of MEARS Technologies patents
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Patents where
Current Assignee
Name
is
MEARS TechnologiesMEARS Technologies
Name
Description
Patent Applicant
Current Assignee
Inventor
Patent Jurisdiction
Patent Number
Date of Patent
‌
US Patent 7700447 Method for making a semiconductor device comprising a lattice matching layer

Patent 7700447 was granted and assigned to MEARS Technologies on April, 2010 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7700447
April 20, 2010
‌
US Patent 7718996 Semiconductor device comprising a lattice matching layer

Patent 7718996 was granted and assigned to MEARS Technologies on May, 2010 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7718996
May 18, 2010
‌
US Patent 7812339 Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures

Patent 7812339 was granted and assigned to MEARS Technologies on October, 2010 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7812339
October 12, 2010
‌
US Patent 7781827 Semiconductor device with a vertical MOSFET including a superlattice and related methods

Patent 7781827 was granted and assigned to MEARS Technologies on August, 2010 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7781827
August 24, 2010
‌
US Patent 9275996 Vertical semiconductor devices including superlattice punch through stop layer and related methods

Patent 9275996 was granted and assigned to MEARS Technologies on March, 2016 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
9275996
March 1, 2016
‌
US Patent 7436026 Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions

Patent 7436026 was granted and assigned to MEARS Technologies on October, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7436026
October 14, 2008
‌
US Patent 7303948 Semiconductor device including MOSFET having band-engineered superlattice

Patent 7303948 was granted and assigned to MEARS Technologies on December, 2007 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7303948
December 4, 2007
‌
US Patent 7517702 Method for making an electronic device including a poled superlattice having a net electrical dipole moment

Patent 7517702 was granted and assigned to MEARS Technologies on April, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7517702
April 14, 2009
‌
US Patent 7586116 Semiconductor device having a semiconductor-on-insulator configuration and a superlattice

Patent 7586116 was granted and assigned to MEARS Technologies on September, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7586116
September 8, 2009
‌
US Patent 7659539 Semiconductor device including a floating gate memory cell with a superlattice channel

Patent 7659539 was granted and assigned to MEARS Technologies on February, 2010 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7659539
February 9, 2010
‌
US Patent 7446002 Method for making a semiconductor device comprising a superlattice dielectric interface layer

Patent 7446002 was granted and assigned to MEARS Technologies on November, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7446002
November 4, 2008
‌
US Patent 7625767 Methods of making spintronic devices with constrained spintronic dopant

Patent 7625767 was granted and assigned to MEARS Technologies on December, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7625767
December 1, 2009
‌
US Patent 7491587 Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer

Patent 7491587 was granted and assigned to MEARS Technologies on February, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7491587
February 17, 2009
‌
US Patent 7435988 Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel

Patent 7435988 was granted and assigned to MEARS Technologies on October, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7435988
October 14, 2008
‌
US Patent 7446334 Electronic device comprising active optical devices with an energy band engineered superlattice

Patent 7446334 was granted and assigned to MEARS Technologies on November, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7446334
November 4, 2008
‌
US Patent 7863066 Method for making a multiple-wavelength opto-electronic device including a superlattice

Patent 7863066 was granted and assigned to MEARS Technologies on January, 2011 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7863066
January 4, 2011
‌
US Patent 7531829 Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance

Patent 7531829 was granted and assigned to MEARS Technologies on May, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7531829
May 12, 2009
‌
US Patent 7928425 Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods

Patent 7928425 was granted and assigned to MEARS Technologies on April, 2011 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7928425
April 19, 2011
‌
US Patent 7880161 Multiple-wavelength opto-electronic device including a superlattice

Patent 7880161 was granted and assigned to MEARS Technologies on February, 2011 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7880161
February 1, 2011
‌
US Patent 7432524 Integrated circuit comprising an active optical device having an energy band engineered superlattice

Patent 7432524 was granted and assigned to MEARS Technologies on October, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7432524
October 7, 2008
‌
US Patent 7514328 Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween

Patent 7514328 was granted and assigned to MEARS Technologies on April, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7514328
April 7, 2009
‌
US Patent 7433729 Infrared biometric finger sensor including infrared antennas and associated methods

Patent 7433729 was granted and assigned to MEARS Technologies on October, 2008 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7433729
October 7, 2008
‌
US Patent 7531850 Semiconductor device including a memory cell with a negative differential resistance (NDR) device

Patent 7531850 was granted and assigned to MEARS Technologies on May, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7531850
May 12, 2009
‌
US Patent 7531828 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions

Patent 7531828 was granted and assigned to MEARS Technologies on May, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7531828
May 12, 2009
‌
US Patent 7586165 Microelectromechanical systems (MEMS) device including a superlattice

Patent 7586165 was granted and assigned to MEARS Technologies on September, 2009 by the United States Patent and Trademark Office.

MEARS Technologies
MEARS Technologies
United States Patent and Trademark Office
United States Patent and Trademark Office
7586165
September 8, 2009
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