SBIR/STTR Award attributes
To meet the U.S. Navy need for high-dynamic-range digitizers for lidar applications, a four-input channel 17-bit dynamic-range application-specific integrated circuit (ASIC) will be developed. Each of the four high-bandwidth input channels will be configured in a fast-in/slow-out architecture, composed of a stacked 512-element switched capacitor array (SCA), capable of 2-ns time-slice sampling, and a digitizer. The Phase I effort will include detailed trade studies, an architecture definition and behavioral circuit performance simulation. Key circuit functions will be designed and simulated. The ASIC will be designed to be less than 1” x 1” and to consume less than 0.5 Watts. In Phase II, the ASIC will be completed, laid out, and fabricated, and a digitizer and processor control prototype system will be assembled, tested, and fully characterized.
