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US Patent 9755017 Co-integration of silicon and silicon-germanium channels for nanosheet devices

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9755017
Date of Patent
September 5, 2017
Patent Application Number
15057439
Date Filed
March 1, 2016
Patent Citations Received
‌
US Patent 11756837 Hybrid nanosheet tunnel-FET/CMOS technology
‌
US Patent 11710780 Semiconductor device fabrication method
0
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US Patent 12015069 Gate-all-around field effect transistor having multiple threshold voltages
0
‌
US Patent 11791400 Semiconductor device
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US Patent 11705503 Semiconductor device including non-sacrificial gate spacers and method of fabricating the same
0
Patent Primary Examiner
‌
Tram H Nguyen
Patent abstract

Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

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