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US Patent 9570464 Method for manufacturing semiconductor device

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
March 18, 2016
Date of Patent
February 14, 2017
Patent Application Number
15074563
Patent Citations Received
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US Patent 11776602 Memory array staircase structure
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US Patent 11943924 Void formation for charge trap structures
0
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US Patent 11923407 Memory device including voids between control gates
0
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US Patent 12002534 Memory array word line routing
0
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US Patent 11985830 Three-dimensional memory device and method
0
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US Patent 11765903 Charge trap structure with barrier to blocking region
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
9570464
Patent Primary Examiner
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Savitr Mulpuri

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