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US Patent 8653672 Three dimensional structure memory

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
8653672
Date of Patent
February 18, 2014
Patent Application Number
12788618
Date Filed
May 27, 2010
Patent Citations Received
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US Patent 12105650 Quasi-volatile system-level memory
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US Patent 12002523 Memory circuit, system and method for rapid retrieval of data sets
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US Patent 12068286 Device with embedded high-bandwidth, high-capacity memory using wafer bonding
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 11670620 Device with embedded high-bandwidth, high-capacity memory using wafer bonding
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US Patent 11675500 High capacity memory circuit with low effective latency
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US Patent 11789644 Memory centric system incorporating computational memory
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US Patent 11844204 Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array
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...
Patent Primary Examiner
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David Lam
Patent abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

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