Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Jing-Cheng Lin0
Po-Hao Tsai0
Date of Patent
February 18, 2014
Patent Application Number
13308162
Date Filed
November 30, 2011
Patent Citations Received
Patent Primary Examiner
Patent abstract
The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.
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