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US Patent 8084830 Nonvolatile semiconductor memory device
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Patent
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Date Filed
September 9, 2009
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Date of Patent
December 27, 2011
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Patent Application Number
12556005
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Patent Citations Received
US Patent 11836277 Secure circuit integrated with memory layer
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Patent Inventor Names
Hiroshi Kanno
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Hideyuki Tabata
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Jun Hirota
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Kenichi Murooka
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
8084830
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Patent Primary Examiner
N. Drew Richards
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