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US Patent 8084830 Nonvolatile semiconductor memory device

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Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
80848300
Patent Inventor Names
Hiroshi Kanno0
Hideyuki Tabata0
Jun Hirota0
Kenichi Murooka0
Date of Patent
December 27, 2011
0
Patent Application Number
125560050
Date Filed
September 9, 2009
0
Patent Citations Received
‌
US Patent 11836277 Secure circuit integrated with memory layer
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Patent Primary Examiner
‌
N. Drew Richards
0
Patent abstract

The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).

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