Patent attributes
The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . . , 50n) responsive to the output of the comparator and to the clock (102), for interpolating time within a clock period from the triggering time of the comparator, said interpolator delivering a time-interpolation output signal as a fine conversion data which is combined to the coarse conversion data for each conversion cycle. Application to an increased resolution without excess power consumption or increased conversion period.
