US Patent 7824962 Method of integrated circuit fabrication

A method for fabricating an integrated circuit including forming a first trench in a rear side of a semiconductor wafer, wherein the first trench has a depth extending partially through a thickness of the semiconductor wafer, coating the rear side with a layer of coating material, including filling the first trench with the coating material, and forming a second trench in a front side of the semiconductor wafer, wherein the second trench is aligned with and has a width less than a width of the first trench, and wherein the second trench has a depth extending at least through a remaining portion of the semiconductor wafer so as to be in communication with the coating material filling the first trench.