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US Patent 7754501 Method for manufacturing ferroelectric capacitor

Patent 7754501 was granted and assigned to Seiko Epson on July, 2010 by the United States Patent and Trademark Office.

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Patent
Patent
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Patent attributes

Current Assignee
Seiko Epson
Seiko Epson
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
77545010
Patent Inventor Names
Tatsuhiro Urushido0
Date of Patent
July 13, 2010
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Patent Application Number
121254180
Date Filed
May 22, 2008
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Patent Citations Received
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US Patent 12108608 Memory devices with dual encapsulation layers and methods of fabrication
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US Patent 12022662 Planar and trench capacitors for logic and memory applications and methods of fabrication
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US Patent 12029043 Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications and methods of fabrication
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US Patent 12069866 Pocket integration process for embedded memory
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US Patent 12108607 Devices with continuous electrode plate and methods of fabrication
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US Patent 11839070 High density dual encapsulation materials for capacitors and methods of fabrication
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US Patent 11839088 Integrated via and bridge electrodes for memory array applications and methods of fabrication
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US Patent 11844203 Conductive and insulative hydrogen barrier layer for memory devices
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...
Patent Primary Examiner
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Tuan N. Quach
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Patent abstract

A method for manufacturing a ferroelectric capacitor includes the steps of: forming a base dielectric film on a substrate, and forming a first plug conductive section in the base dielectric film at a predetermined position; forming, on the base dielectric film, a charge storage section formed from a lower electrode, a ferroelectric film and an upper electrode; forming a stopper film from an insulation material that covers the charge storage section; forming a hydrogen barrier film that covers the stopper film; forming an interlayer dielectric film on the base dielectric film including the hydrogen barrier film; forming, in the interlayer dielectric film, a first contact hole that exposes the first plug conductive section; forming a second contact hole that exposes the upper electrode of the charge storage section by successively etching the interlayer dielectric film, the hydrogen barrier film and the stopper film by using a resist pattern as a mask, and then removing the resist pattern by a wet cleaning treatment; forming an adhesion layer from a conductive material having hydrogen barrier property inside the second contact hole in a manner to cover an upper surface of the upper electrode; forming a second plug conductive section inside the first contact hole; and forming a third plug conductive section inside the second contact hole, wherein the stopper film is formed from a material having a lower etching rate for a cleaning liquid used for the wet cleaning treatment to remove the resist pattern than an etching rate of the hydrogen barrier film for the cleaning liquid.

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