US Patent 7636267 Semiconductor memory device

In a semiconductor memory device employing shared type sense amplifiers, entry is made to the test mode, and transfer gates, pre-charge circuits, and sense amplifiers used in the shared type sense amplifiers are controlled individually. An object bit line is placed in the high impedance state. The opposing sense amplifier is left active to place an adjacent bit line in the low impedance state. If there is a bit-line to bit-line short, data on the object bit line in the high impedance state is inverted from the adjacent bit line in the low impedance state. The bit-line to bit-line short can be detected by reading the inverted data.